Integrated circuit memories are organized into one or more arrays each including a matrix of rows and columns, with a memory cell located at each intersection of a row and a column. When accessed during a read cycle, the memory decodes an address to enable one row line. The memory cells on the enabled row line provide their contents onto bit lines, or more commonly, onto differential bit line pairs. Column decoding is used to select a subset of the bit line pairs to couple to one or more differential data line pairs. A sense amplifier coupled to each data line pair detects a logic state of the differential signal and amplifies it. The amplified signal may then be provided to an output terminal of the memory, or further decoding may take place.
The speed at which the decoding takes place together with the sense time determine the overall speed of the memory. To help improve the speed of the memory, the sense time may be reduced. In recent years the differential sensing technique has normally been used to increase the speed of high-speed memories.
At the same time sense amplifiers must correctly sense the state of the selected memory cell. Sense amplifiers for differential data lines, however, may also be susceptible to a problem known as sense line disturb. Sense line disturb occurs when a differential sense amplifier is precharged to a power supply voltage, which causes the sense amplifier to be unable to resolve the logic state for an extended period of time. In worst case conditions, the logic state may also be improperly recognized. For most points in the manufacturing process window, the sense amplifier may be able to recover. However the sense amplifier may eventually fail to resolve the correct logic state of the memory cell. The result is that many integrated circuits will have to be scrapped even though they have been processed within normal manufacturing variances.
Moreover, memory densities have grown over time, generally obeying “Moore's Law”. While there may eventually be absolute physical limitations to memory density, they have not yet been encountered. Thus it would be desirable for a sense amplification scheme to be able to accommodate higher densities without re-design.
Therefore what is needed then is a memory with fast sense time, immunity to sense line disturb, and which may be easily scaled to higher densities. A memory according to the present invention provides such benefits, and these and other features and advantages will be made clearer in view of the drawings taken in conjunction with the detailed description.